module  dds_sine                        //K=300
(
input clkfc,rst_n,
input [31:0]date_k,
output [13:0]date_sine
);
reg[31:0]add_sine;
always@(posedge clkfc,negedge rst_n)
begin
 if(!rst_n)
  add_sine<=32'd0;
 else
  begin
  add_sine<=add_sine+date_k;
  end
end
wire [11:0]add_sine_12;
assign add_sine_12=add_sine[31:20];
sinrom_add12_date14	sinrom_add12_date14_inst (
.address ( add_sine_12 ),
.clock ( clkfc ),
.q ( date_sine )
);
endmodule 